Senior EMC / Hardware Engineer
You are hiring a senior-level hardware design engineer who specializes in EMC troubleshooting and isolated PoE power design for networking and wireless products. This is a hands-on design role, not a compliance test operator. Atheer ACT is a Saudi deep-tech telecommunications company building carrier-grade 60 GHz and mmWave wireless infrastructure for high-throughput backhaul and enterprise connectivity. What they will do: This engineer will be responsible for diagnosing and fixing a live EMC compliance failure on the PoE port of an outdoor wireless radio product. Their work will directly impact the success of the current certification cycle. Key responsibilities include: Analyze EMC failure plots and identify root causes quickly. Redesign isolated PoE PD converters (IEEE 802.3bt Type 3/4). Design and tune magnetics: flyback transformers, common-mode chokes, isolation barriers. Optimize PCB layout for EMC performance: grounding, isolation, filter placement. Reduce conducted emissions on telecom ports (CISPR 32 / EN 55032 using ISN). Guide the product through full EMC certification, including retests. Work closely with hardware, RF, and compliance teams. Must-have experience: 8+ years of experience designing PoE power stages, solving EMC failures, and shipping telecom or networking hardware through certification. Bachelor's degree or higher in Electrical Engineering, Electronics, or a related field. Isolated PoE PD converter design compliant with IEEE 802.3bt Type 3 or Type 4. Flyback topology design and transformer construction. Common-mode choke selection under DC bias. CISPR 32 / EN 55032 conducted emissions testing on telecom ports using ISN. PCB layout for EMC performance.
(تازہ ترین نوکریاں، سلیبس اور ٹیسٹ کی تیاری کی مکمل معلومات)
Preparing
2910
Duration
Permanent
Focus areas
People Also Ask (FAQs)
What is the last date to apply for Senior EMC / Hardware Engineer?
The official closing date is 2027-02-13. Apply early to avoid the last-day portal rush.
How do I apply for Senior EMC / Hardware Engineer?
Use the official apply link on this page to submit your application. A step-by-step how-to-apply guide for this job is also linked below.
Is there negative marking in the Atheer ACT test?
The marking rule is announced per test in the advertisement and roll-number-slip instructions. Many MCQ screening tests have no negative marking, but always verify it for your specific test.
What is the passing marks for this test?
The official passing marks are generally 50%, but merit is competitive — scoring above 75% is a safer target to secure an interview call.
How can I prepare for the Senior EMC / Hardware Engineer test?
Prepare with the free subject-wise MCQs, past papers and timed mock tests on PrepPro Academy — every question includes the answer with an explanation. Focus areas: EMC Troubleshooting, Power over Ethernet (PoE), Hardware Design, PCB Layout, RF Engineering.
Quick start
Review the job summary, then jump into prep with the same flow used for exam starts.